San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...

With so many ASIC designers moving over to FPGAs for implementation, FPGA tool flows are looking more and more like ASIC flows. Case in point: Actel's Libero IDE 6.2 adds native static timing analysis ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus ™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity ...

Static timing analysis (STA) is used throughout chip design. It’s employed for the creation of basic constraints in synthesis, for block- and chip-level timing closure in physical implementation, and ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).