电子工程专辑

如何用Python写Verilog？

事情是这样的，SoC工程师的一项典型工作就是集成。俗称连连看。 当然除了连连看还有一些集成级的代码需要设计，比如CRG，regfile，ahb/apb/local bus decoder，axi bus matrix/network等等。这些代码很多是有vendor提供工具生成，或者用脚本生成。集成工作我们前面介绍的 ...
Electronics Weekly

Using Verilog-A simulation in analogue design

A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are ...
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
EDN

Innologic offers hierarchical Verilog simulator

SAN JOSE, Calif. — InnoLogic Systems Inc. is calling its ESP-BV the first commercial hierarchical Verilog simulator, a binary simulator that uses the company's “hierarchical compression” technology.
Hackaday

Learning Verilog For FPGAs: The Tools And Building An Adder

Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...